Solutions implementing a post-processor after channel detection are currently used in communication systems, also for possible use in signal storage.
The diagram in FIG. 1 illustrates the typical concatenation between an encoder B which receives an input digital signal organised in blocks of length k and outputs a coded signal organised in blocks comprising n=k+r bits. Generally, an error correction code is a binary block code (n, k) based on an ad hoc parity check matrix H (or polynomial p(D)).
A typical partial response channel PR is shown cascaded to block encoder B.
Creating an optimal detector is not always possible in encoding. This is because the detector is identified by the concatenated effect of the channel and the code trellises. For this reason, sub-optimal implementations are used for decoding. These comprise a dual-stage decoder with post-processor exploiting the knowledge of error events of the channel.
A typical example of decoder based on the use of a post-processor of the traditional type is shown in FIG. 2.
The received signal r(n) is sent to a Viterbi detector VD (or any detector implementing an similar algorithm) so to generate a signal u(n). Before being used as a decoded output signal u′(n), the signal u(n) is passed through a module, herein indicated as SCEC, which implements a syndrome check (SC) and error correction (EC) function.
The SCEC module is controlled by a signal generated by a bank of filters F1, F2, . . . , FN according to an error sequence e(n) generated in a node S. The node S sums with sign (i.e. subtracts) the input signal r(n), delayed via a delay line DL, and the signal u(n) subjected to the filtering function FD corresponding to the considered PR class. The delay line DL compensates the delays set to the signal which reaches the node S with a negative sign by effect of the processing of modules VD and FD.
In the example shown in FIG. 2, the post-processor SCEC receives hard decisions u(n) from the Viterbi detector VD and subjects the respective encoded words to syndrome checking.
If the result of the check is negative, the post-processor attempts to correct the signal on the basis of the syndrome and the most likely error event list. Essentially, the post-processor re-computes the most likely sequence (the sequence closest to the received sequence), which is a channel sequence and which also satisfies the syndrome check. An example of this way of operation is illustrated in detail in WO-A-00/07187.
As shown in FIG. 2, the most frequent channel error events are compared with the error sequence e(n) via the bank of matched filters F1, F2, . . . , FN. The post-processor selects the best correlation between the error sequence and one of the error events described in the filters. The syndrome value determines the type and position of the error events capable of correcting the wrong received codeword.
Other examples of post-processors implementing a filter bank matched to the most likely error events are described in U.S. Pat. Nos. 6,185,173 and 6,185,175.
Another similar post-processor, whose operation is based on the premise of considering and processing reliability information as independent, is described in U.S. Pat. No. 6,061,823.
The post-processor decoders described above are capable of providing entirely satisfying performance in numerous operative contexts. However they are intrinsically vulnerable with respect to correction errors and, particularly, to the possible propagation of such errors.